Wavecom GX64 Service Manual

INTEGRATORS’ MANUAL GR64 GSM/GPRS Wireless CPU® Reference: WI_DEV_GR64_UGD_001 Version: 002 Date: 2007/02/06

1 Introduction 1.1 Target Users The GR64 Wireless CPU®s are designed to be integrated into machine-to-machine or man-to-machine communications appl

10 Regulatory Notices The GR64 described in this manual conforms to the Radio and Telecommunications Terminal Equipment (R&TTE) directive 99/5

This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement. Ce document est la

This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement. Ce document est la

This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement. Ce document est la

DEVELOPERS KIT This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement. Ce d

11 Introduction to the Universal Developer’s Kit The Wavecom universal developer’s kit (UDK) is designed to get the integrator started quickly. It

GR64 Integrators’ Manual Page: 106/106 This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior

1.4 Notation The following symbols and admonition notation are used to draw the reader’s attention to notable or crucially-important information.

1.5 Abbreviations Abbreviation Explanation AMR Adaptive Multi Rate CBM Cell Broadcast Message CPS Charging Power Supply CSD Circuit Switched D

Abbreviation Explanation ME Mobile Equipment (Wireless CPU® without SIM card) MMCX Micro Miniature Coax MO Mobile Originated MS Mobile Station (

2 GR64 Wireless CPU® 2.1 About the GR64 The Wavecom Gx64 family of devices are Quad Band GSM/GPRS Wireless CPU®s operating in the GSM 850/900/1800/

2.2 Wireless CPU® in a Communication System Figure 1 and Figure 2 illustrate the main blocks of a wireless communication system using the Wireless C

SIMSIMGSMENGINEGSMENGINEDCEDCEDTEDTESYSTEM INTERFACESTATUS &RESPONSECOMMAND& CONTROLMSGSMNETWORKDCPOWERGR64SIMSIMGSMENGINEGSMENGINEDCEDCEDTE

2.3 Features The Wireless CPU® performs a set of telecom services (TS) according to 3GPP release 99 and ITU-T. The functions of the Wireless CPU® a

• CBM (cell broadcast message); a service in which a message is sent to all subscribers located in one or more specific cells in the GSM network (fo

GR64 Integrators’ Manual Page: 19/106 This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior

GR64 Integrators’ Manual Page: 2/106 This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior w

The power consumption figures shown represent typical average current for maximum transmitted power, single uplink (transmit) slot, and single downl

2.4 Service and Support 2.4.1 Web Pages Visit the Wavecom extranet web site for the following information: • Where to buy Wireless CPU®s or for r

Make sure to order the M2M Wireless CPU®(s) that are applicable to the needs of the organization. Also, ensure that the integrator have computer or

2.6.2 Radio Frequency (RF) Exposure and SAR The Wireless CPU® device is a low-power radio transmitter and receiver (transceiver). When it is turned

2.6.4 Disposal of Old Electronic Equipment This symbol on the product or on its packaging indicates that this product shall not be treated as househ

INTEGRATING THE WIRELESS CPU® This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written

3 Mechanical Description 3.1 Interface Description The pictures below show the mechanical design of the Wireless CPU® along with the positions of t

Please note the following: • Mounting holes positioned at the corners make it possible to securely bolt the Wireless CPU® into the application. •

3.3 Physical Dimensions Figure 6: Dimensions of the Wireless CPU® (Integrated SIM variant) This document is the sole and exclusive property of W

Figure 7: Dimensions of the Wireless CPU® (Legacy variant) Measurements are given in millimetres. See also Technical Data, in Section 9. This do

Revision History Edition Change Information First First Edition Second Updated FCC marking requirements Signal connectivity table updated Modifie

4 System Connector Interface 4.1 Overview Electrical connections to the Wireless CPU® (except the antenna), are made through the System Connector I

Table 2: Pin Assignments Pin Name Direction Function PIN Req 1 VCC Input DC power Yes 2 GND - Ground Yes 3 VCC Input DC power Yes 4 GND - Gr

Pin Name Direction Function PIN Req 35 TX_ON Output Transmit indication RI Output Ring Indicator 36 GPIO8 In/Out General purpose IO DTR1

4.2 Dealing with Unused Pins Integrators applications may connect all of the GR64 signals pins, or just those necessary for minimal operation, or mo

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4.3 General Electrical and Logical Characteristics The core digital IO is based upon 1.8V technology in the Baseband chipset. All external IO signa

4.3.1 Level Translator Interfaces Two different level translator circuits are implemented in GR64. The ‘common’ interface is used on all level-tran

4.3.1.2 I2C Level Translator Interface Because of the nature of the I2C interface signals, SDA (data) & SCL (clock), they utilize a different ty

4.4.1 Analogue Ground (AREF) AREF is the return signal, or analogue audio reference, for AUXI and AUXO. These two signals provide a single-ended au

4.5 Regulated Power Supply Input (VCC) Pin Name Direction Function 1 VCC Input DC power 3 VCC Input DC power 5 VCC Input DC power 7 VCC Input D

Contents 1 Introduction ... 10 1.1 TARGET USERS...

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4.6 Voltage Reference (VREF) Pin Name Direction Function 34 VREF Input (Output) Core voltage reference GR64 provides a voltage reference inter

Table 5: Interface implementation description GR64 variant Application Logic Voltage Level (VLOGIC) Implementation Requirements The application must

4.6.2 VREF as an Input to the Wireless CPU® The GR64002 variants provide VREF as a reference input for the host side logic. This enables users of v

GR64 Integrators’ Manual Page: 44/106 Figure 12: GR64 Charger Implementation The GR64 Wireless CPU® supports only one mode of charging, micropro

During microprocessor supervised mode, the GR64 takes a current-limited voltage source at the CHG_IN pin to implement constant-current charging of a

level if it subsequently falls below VCC by 50 mV. If the relative voltage of CHG_IN goes invalid and remains invalid for the duration of the detect

The lithium ion battery is free from the so-called memory effect, a phenomenon associated with nickel cadmium in which the apparent battery capacity

• monitor battery temperature during charging using a thermistor placed on or near the battery wired to an ADC input on the Wireless CPU® Li-Ion b

4.8 Powering the Wireless CPU® ON and OFF (ON/OFF) Pin Name Direction Function 14 ON/OFF Input Device on/off control The ON/OFF description

2.6.4 DISPOSAL OF OLD ELECTRONIC EQUIPMENT ... 24 2.7 PRODUCT MARKING...

Initially, power is supplied to the VCC pins. The presence of power raises the ON/OFF through a pull-up resistor to VCC potential. In order to powe

4.8.2 Turning the Wireless CPU® Off Figure 15: Power Off timing for GR64001 Failure to implement the proper shut down procedure could result in

The RTC can continue to operate even though VCC is removed, provided that a sufficiently charged backup device is connected to the VRTC. Refer to

4.9 Analogue Audio Pin Name Direction Function 53 MICIP Input Microphone input positive 54 MICIN Input This document is the sole and excl

4.9.1 Auxiliary Audio to Wireless CPU® (AUXI) AUXI is a single-ended auxiliary analogue audio input to the Wireless CPU®. Internally, the signal is

4.9.2 Auxiliary Audio from Wireless CPU® (AUXO) AUXO is a single-ended auxiliary analogue audio output from the Wireless CPU® and may be used to dri

4.9.3 Microphone Signals (MICIP, MICIN) MICIP and MICIN are balanced differential microphone input pins. These inputs are compatible with an electr

4.9.4 Speaker Signals (EARP, EARN) EARP and EARN are the speaker output signals. These are differential-mode outputs. With a full-scale PCM input

4.10 PCM Digital Audio (SSP) Pin Name Direction Function 48 SSPDFM Output Serial PCM data from Wireless CPU® to host 47 SSPDTM Input Seria

4.10.1 PCM Data Format The PCM digital audio interface for GR64 is based upon the Texas Instruments SSI standard. The SSP interface can be programm

4.9.4 SPEAKER SIGNALS (EARP, EARN)... 57 4.10 PCM DIGITAL AUDIO (SSP) ...

MSBMSBLSBLSBLSBLSBMSBMSBFrame nFrame n-1 Frame n+1SSPCLKSSPFSSSPDFMSSPDTMMSBMSBLSBLSBLSBLSBMSBMSBFrame nFrame n-1 Frame n+1SSPCLKSSPFSSSPDFMSSPDTM Fi

4.11 Serial Data Interfaces The serial channels consist of two UARTs and a USB port. These provide communication links to the application or access

UART1 is a full featured Universal Asynchronous Receiver Transmitter providing full-duplex asynchronous communication. UART1 has the following featur

4.11.1.1 Serial Data Signals (DTM1, DFM1) The default baud rate of the UARTs is auto-baud. Baud rates of between 600 bauds to 460k bauds are possib

4.11.1.3 Control Signals (DTR1, DSR1, DCD1, RI) 4.11.1.3.1 Data Terminal Ready (DTR1) DTR indicates that the DTE is ready to receive data. It also

4.11.2 UART3 (DTM3, DFM3) The reason UART2 is skipped is that GR64 does not support more than two UART interfaces. The removed interface was repres

4.11.3 USB Pin Name Direction Function 45 USBDP In/Out USB data positive 46 USBDN In/Out USB data negative 49 VUSB Input USB DC power T

• Firmware ability to wake up and reset a suspended device • 8, 16, 32, and 64-byte FIFO sizes for non-isochronous transfers • 64, 256, 512, an

This SIM interface allows the use of 3 V and 1.8 V SIM cards (5V is unsupported). The Wireless CPU® automatically detects the SIM type, switching t

4.12.1 SIM Detection (SIMDET) SIMDET is used to determine whether a SIM card has been inserted into or removed from the SIM card holder. The integra

6.2 SIM CARD ... 86 6.3 ANTENNA ...

4.13 Service/Programming Pin Name Direction Function 58 SERVICE Input Flash programming enable signal The SERVICE interface is flash program

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4.15 LED Pin Name Direction Function 33 LED Output LED control signal The LED interface is intended to operate a status LED, which can be pr

4.16 General Purpose IO Pin Name Default Alternate function 21 GPIO1 GPIO1 22 GPIO2 GPIO2 23 GPIO3 GPIO3 24 GPIO4 GPIO4 13 GPIO5 AD

• Polarity (inversion) • Internal pull-up resistors The internal pull-up resistors are applied on the Wireless CPU® side of the level translato

4.16.2 LED/IO6 Capabilities The LED function pin can be used as a general purpose digital I/O when the flashing LED function is not required. Howeve

Figure 27: ADC sharing arrangement ADC sampling frequency and sampling source selection can be set up and controlled with AT-commands by the user

High-level Input Voltage ADC output=3FFh 2.45 2.59 V ADC Clock (ADCLK) 260 325 390 kHz ADC Conversion Time 12 ADCLKADC Sample Delay

4.18 I2C Serial Control Bus Pin Name Direction Function 29 SDA In/Out I2C data 30 SCL Output I2C clock The I2C interface comprises two signal

Fast-mode signal characteristics Parameter Min Typ Max Unit SCL clock frequency 0 400 kHz μs LOW period of the SCL clock 1.3 μs HIGH pe

9.5 ENVIRONMENTAL SPECIFICATION... 97 10 Regulatory Notices ...

Figure 28: Recommended circuitry for a TX_ON implementation 4.20 Real Time Clock The real-time clock (RTC) is driven by a 32.768 kHz clock from

4.20.1 Real Time Clock Backup Supply (VRTC) Pin Name Direction Function 25 VRTC Input DC supply for real time clock VRTC provides an input

In the backup condition the RTC block will function to as low as 1.1V on the VRTC pin. The RTC draws 10µA typically during powered backup (15µA max)

4.20.2 RTC Alarm (ALARM) Pin Name Direction Function 50 ALARM Output RTC Alarm The ALARM signal is only available on GR64002. NOTE The Ala

5 Antenna Connector The Wireless CPU®’s antenna connector allows transmission of the radio frequency (RF) signals from the Wireless CPU® to an exter

6 Hints for Integrating the Wireless CPU® This chapter gives the integrator advice and helpful hints on how to integrate the Wireless CPU® into the

6.2 SIM Card Before handling any SIM card, users should ensure that they are not charged with static electricity. Use proper precautions to avoid

6.4 Installation of the Wireless CPU® 6.4.1 Where to Install the Wireless CPU® The following conditions need to be taken into consideration when de

6.4.1.3 Connection of Components to Wireless CPU® The integrator is responsible for the final integrated system. Incorrectly designed or installed,

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Table of Figures Figure 1: Main Blocks in a Wireless System (embedded application)... 15 Figure 2: Main Blocks in a

6.5.2 Antenna Type Users should ensure that they choose the right type of antenna for the Wireless CPU®. The antenna must be designed for the freq

Minimize the use of extension cables, connectors and adapters. Each additional cable, connector or adapter will result in additional loss of signal

7 Embedded Applications The Wireless CPU® has the capability to store and run customer written code in the form of a script during the processor’s i

7.2.1 Limitations Since the Wireless CPU® is processing the script using its own memory, limitations are placed onto the scripts that are run. A dir

8 TCP/IP Stack An on board IP/TCP/UDP stack has been integrated into the software negating the need for the customer to implement one in their own c

9 Technical Data 9.1 Mechanical Specifications Refer to Figure 3 & Figure 4 for reference to mechanical features. Mechanical Feature Variant

9.2 Power supply voltage, normal operation Parameter Mode Limit Nominal 3.6 V Min 3.2 V Max 4.5 V Absolute maximum voltage range -0.3 to 6.5 V VC

9.4 SIM card Parameter 1.8V 3.0V 5.0V External SIM support Yes Yes No Integrated SIM support (optional) Yes Yes No 9.5 Environmental S

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Test Case Test Summary Ref Standard Sinusoidal Vibration Freq: 10-60 Hz, constant displacement ≡±0.35mm Freq : 60-500 Hz, constant acceleration ≡